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july 2006 rev 8 1/30 1 m41t81 serial access real-time clock with alarm feature summary counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 32khz crystal oscillator integrating load capacitance (12.5pf) providing exceptional oscillator stability and high crystal series resistance operation serial interface supports i 2 c bus (400khz protocol) ultra-low battery supply current of 0.6 a (typ@3v) 2.0 to 5.5v clock operating voltage automatic switch -over and deselect circuitry (for 3v application select m41t81s data sheet) power-down time stam p (ht bit) allowing determination of time elapsed in battery back up programmable alarm and interrupt function (valid even during battery back-up mode) accurate programmable watchdog timer (from 62.5ms to 128s) software clock calibration to compensate crystal deviation due to temperature operating temperature of ?40 to 85c ecopack? package available 8 1 so8 (m) 8-pin soic www.st.com
contents m41t81 2/30 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
m41t81 list of tables 3/30 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. so8 ? 8-lead plastic small outline (150 m ils body width), package mechanical data. . . . . 27 table 15. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
list of figures m41t81 4/30 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. 8-pin soic (m) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 15. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 17. so8 ? 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
m41t81 summary description 5/30 1 summary description the m41t81 is a low power serial rtc with a built-in 32.768khz oscilla tor (external crystal controlled). eight bytes of the sram (see table 2: clock register map on page 14 ) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 12 bytes of sram provide status/control of alarm, watchdog and square wave functions. addresses and data are transferred serially via a two line, bi-directional i 2 c interface. the built-in address register is incremented automatically after each write or read data byte. the m41t81 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. the energy needed to sustain the sram and clock operations can be supplied by a small lithium button supply when a power failure occurs. functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupts, watchdog timer and programmable square wave output. the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. the m41t81 is supplied in an 8-pin soic. figure 1. logic diagram scl v cc m41t81 v ss sda irq/ft/out/sqw v bat xi xo ai04613
summary description m41t81 6/30 figure 2. 8-pin soic (m) connections table 1. signal names xi oscillator input xo oscillator output irq /out/ft/sqw interrupt / out put driver / frequency test / square wave (open drain) sda serial data input/output scl serial clock input v bat battery supply voltage v cc supply voltage v ss ground nc no connect nf no function 2 3 45 6 8 7 1 irq/ft/out/sqw sda v bat scl v ss xo xi v cc m41t81 ai04769
m41t81 summary description 7/30 figure 3. block diagram 1. open drain output 2. square wave function has the highest priority on irq /ft/out/sqw output. 3. v so = v bat ? 0.5v (typ) ai04616 real time clock calendar rtc w/alarm & calibration watchdog square wave frequency test output driver irq/ft/out/sqw (1,2) internal power sqwe afe sda scl v cc compare i 2 c interface 32khz oscillator v bat crystal v so (3) write protect ft out
operation m41t81 8/30 2 operation the m41t81 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 20 bytes contained in the device can then be accessed sequentially in the following order: 1 st byte: tenths/hundredths of a second register 2 nd byte: seconds register 3 rd byte: minutes register 4 th byte: century/hours register 5 th byte: day register 6 th byte: date register 7 th byte: month register 8 th byte: year register 9 th byte: control register 10 th byte: watchdog register 11 th - 16 th bytes: alarm registers 17 th - 19 th bytes: reserved 20 th byte: square wave register the m41t81 clock continually monitors v cc for an out-of-tolerance condition. should v cc fall below v so , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at th is time to prevent erroneous data from being written to the device from a an out-of-tolerance system. the device also automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . for more information on battery storage life refer to application note an1012. 2.1 2-wire bus characteristics the bus is intended for communication between di fferent ics. it consists of two lines: a bi- directional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock line is high, will be inte rpreted as control signals. accordingly, the following bus conditions have been defined: 2.1.1 bus not busy both data and clock lines remain high.
m41t81 operation 9/30 2.1.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 2.1.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. 2.1.4 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? th e device that controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? 2.1.5 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition.
operation m41t81 10/30 figure 4. serial bus data transfer sequence figure 5. acknowledgement sequence 2.2 read mode in this mode the master reads the m41t81 slave after setting the slave address (see figure 7 on page 11 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w =1). at this point the master transmitter becomes the master receiver. the data byte which was addressed will be transmitted and the master re ceiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41t81 slave transmitter will now pl ace the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ?an+2.? this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-13h). note: this is true both in read mode and write mode. ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
m41t81 operation 11/30 an alternate read mode may also be implemented whereby the master reads the m41t81 slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 8 on page 11 ). figure 6. slave address location figure 7. read mode sequence figure 8. alternative read mode sequence ai00602 r/w slave address start a 01000 11 msb lsb ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
operation m41t81 12/30 2.3 write mode in this mode the master transmitter transmits to the m41t81 slave receiver. bus protocol is shown in figure 9 on page 12 . following the start condition and slave address, a logic '0' (r/w =0) is placed on the bus and indicates to the addressed device that word address ?an? will follow and is to be written to the on-chip add ress pointer. th e data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge cloc k. the m41t81 slave receiver will send an acknowledge clock to the master transm itter after it has received the slave address see figure 6 on page 11 and again after it has received the word address and each data byte. 2.4 data retention mode with valid v cc applied, the m41t81 can be accessed as described above with read or write cycles. should the supply voltage decay , the power input will be switched from the v cc pin to the battery when v cc falls below the battery back-up switchover voltage (v so ). at this time the clock registers will be maintained by the attached battery supply. on power- up, when v cc returns to a nominal value, write protection continues for t rec (see figure 10 on page 23 , table 11 on page 24 ). for a further, more detailed review of lifetime calculations, please see application note an1012. figure 9. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
m41t81 clock operation 13/30 3 clock operation the 20-byte register map (see table 2 on page 14 ) is used to both set the clock and to read the date and time from the clock, in a bina ry coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. note: the tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d6 and d7 of clock register 03h (century/hours register) contain the century enable bit (ceb) and the century bit (cb). se tting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 thr ough d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month and years. the ninth clock register is the control register (this is described in the clock calibration section). bit d7 of register 01h contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a signif icant amount of time on the shelf, the oscillato r may be stopped to reduce curr ent drain. when reset to a '0' the oscillator restarts within one second. the eight clock registers may be read one byte at a time, or in a sequential block. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a trans ition of data during the read. 3.1 power-down time-stamp when a power failure occurs, the ht bit will automa tically be set to a '1.' this will prevent the clock from upda ting the timekeeper ? registers, and will allow the user to read the exact time of the power-down event. resetting the ht bit to a '0' will allow the clock to update the timekeeper registers with the current time. for more information, se e application note an1572. 3.2 clock registers the m41t81 offers 20 internal registers which contain clock, alarm, watchdog, flag, square wave and control data. these registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as biport ? cells). the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resu me either due to a st op condition or when the pointer increments to any non-clock address (08h-13h). clock and alarm registers store data in bcd. control, watchdog and square wave registers store data in binary format.
clock operation m41t81 14/30 table 2. clock register map (1) addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h ceb cb 10 hours hours (24 hour format) century/ hours 0-1/00-23 04h 0 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out ft s calibration control 09h 0 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe abe al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 ht ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 0 0 0 flags 10h 0 0 0 0 0 0 0 0 reserved 11h 0 0 0 0 0 0 0 0 reserved 12h 0 0 0 0 0 0 0 0 reserved 13h rs3 rs2 rs1 rs0 0 0 0 0 sqw 1. keys: s = sign bit ft = frequency test bit st = stop bit 0 = must be set to '0' bmb0-bmb4 = watchdog multiplier bits ceb = century enable bit cb = century bit out = output level abe = alarm in battery back-up mode enable bit afe = alarm flag enable flag rb0-rb1 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits wdf = watchdog flag (read only) af = alarm flag (read only) sqwe = square wave enable rs0-rs3 = sqw frequency ht = halt update bit
m41t81 clock operation 15/30 3.3 calibrating the clock the m41t81 is driven by a quartz contro lled oscillator with a nom inal frequency of 32,768hz. the devices are te sted not exceed 35 ppm (par ts per million) oscillator frequency error at 25 o c, which equates to about +1.9 to ?1.1 minutes per month (see figure 10 on page 16 ). when the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25c. the oscillation rate of crystals changes wi th temperature. the m4 1t81 design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di vide by 256 stage, as shown in figure 11 on page 16 . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register 08h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only th e first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register (see figure 11 on page 16 ). assuming that the oscillator is running at exac tly 32,768hz, each of t he 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41t81 may require. the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, ?timekeeper ? calibration.? this allows the designer to give the end user the ability to calibrate the clock as the enviro nment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that accesses the calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of the irq /ft/out/sqw pin. the pin will toggle at 51 2hz, when the stop bit (st, d7 of 01h) is '0,' the frequency test bit (ft, d6 of 08h) is '1,' the alarm flag enable bit (afe, d7 of 0ah) is '0,' and the square wave enable bit (sqwe, d6 of 0ah) is '0' and the watchdog register (09h = 0) is reset. any deviation from 512hz indicates the degree and direction of oscillato r frequency shift at the test temperature. for example, a reading of 512.010124hz would indicate a +20 ppm oscillator frequency erro r, requiring a ?10 (xx001010) to be loaded into the calibration byte for correction. note that setting or changi ng the calibration byte does not affect the frequency test output frequency.
clock operation m41t81 16/30 the irq /ft/out/sqw pin is an open drain output which requires a pull-up resistor to v cc for proper operation. a 500-10k resistor is recommended in order to control the rise time. the ft bit is cleared on power-down. figure 10. crystal accuracy across temperature figure 11. clock calibration ai07888 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = ?0.036 ppm/ c 2 0.006 ppm/ c 2 k ? f = k x (t ? t o ) 2 f t o = 25 c 5 c ai00594b normal positive calibration negative calibration
m41t81 clock operation 17/30 3.4 setting alarm clock registers address locations 0ah-0eh contain the alarm settings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. it can also be programmed to go off while the m41t81 is in the battery back-up mode to serve as a system wake-up call. bits rpt5-rpt1 put the alarm in the repeat mode of operation. table 3 on page 18 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set (and sqwe is '0.'), the alarm condition activates the irq /ft/out/sqw pin. note: if the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to oc cur until the address po inter is moved to a different address. it should also be noted that if the last address written is the ?alarm seconds,? the address pointer will increment to the flag address, causing this situation to occur. the irq /ft/out/sqw output is cleared by a read to the flags register as shown in figure 12 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq /ft/out/sqw pin can also be activated in the battery back-up mode. the irq /ft/out/sqw will go low if an alarm occu rs and both abe (alarm in battery back-up mode enable) and afe are set. figure 13 illustrates the back-up mode alarm timing. figure 12. alarm interrupt reset waveform irq/ft/out/sqw active flag 0fh 0eh 10h high-z ai04617
clock operation m41t81 18/30 figure 13. back-up mode alarm waveform 3.5 watchdog timer the watchdog timer can be used to detect an out-of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplication of the five-bit multiplier valu e with the resolution. (for example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). if the processor does not reset the timer within the specified period, the m41t81 sets the wdf (watchdog flag) and generates a watchdog interrupt. the watchdog timer can be reset by having the microprocessor perform a write of the watchdog register. the time-out period then starts over. should the watchdog timer time-out, a value of 00h needs to be written to the watchdog register in order to clear the irq /ft/out/sqw pin. this will al so disable the watchdog function until it is again programmed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set, the frequency test function is activated, and the sqwe bit is '0,' the watchdog function prev ails and the frequency test function is denied. table 3. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 1 1 0 0 0 once per day 1 0 0 0 0 once per month 0 0 0 0 0 once per year v cc irq/ft/out/sqw abe and afe bits af bit in flags register high-z v so trec ai05663
m41t81 clock operation 19/30 3.6 square wave output the m41t81 offers the user a programmable square wave function which is output on the sqw pin. rs3-rs0 bits located in 13h establish the square wave output frequency. these frequencies are listed in ta bl e 4 . once the selection of the sqw frequency has been completed, the irq /ft/out/sqw pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. 3.7 century bit bits d7 and d6 of clock register 03h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. table 4. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none- 000132.768khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
clock operation m41t81 20/30 3.8 output driver pin when the ft bit, afe bit, sqwe bit, and watchdog register are not set, the irq /ft/out/sqw pin becomes an output driver that reflects the contents of d7 of the control register. in other words, when d7 (out bit) and d6 (ft bit) of address location 08h are a '0,' then the irq /ft/out/sqw pin will be driven low. note: the irq /ft/out/sqw pin is an open drain which requires an external pull-up resistor. 3.9 preferred initial power-on default upon initial application of power to the device, the following register bits are set to a '0' state: watchdog register; afe; abe; sqwe; and ft. th e following bits are set to a '1' state: st; out; and ht (see table 5 on page 20 ). table 5. preferred default values condition st ht out ft afe sqwe abe watchdog register (1) 1. bmb0-bmb4, rb0, rb1. initial power-up (2) 2. state of other control bits undefined. 11100 0 0 0 subsequent power-up (with battery back-up) (3) 3. uc = unchanged uc 1 uc 0 uc uc uc 0
m41t81 maximum rating 21/30 4 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. caution: negative undershoots below ?0.3 volts are not allowed on any pin while in the battery back- up mode table 6. absolute maximum ratings sym parameter value unit t stg storage temperature (v cc off, oscillator off) soic ?55 to 125 c v cc supply voltage ?0.3 to 7 v t sld lead solder temperature for 10 seconds lead-free lead finish (1) 1. for so8 package, lead-free (pb-free) lead finish: reflow at peak temperature of 260c (total thermal budget not to exceed 245c for greater than 30 seconds). 260 c standard (snpb) lead finish (2) 2. for so8 package, standard (snpb) lead finish: reflow at peak temperature of 240c (total thermal budget not to exceed 180c for between 90 to 150 seconds). 240 c v io input or output voltages ?0.3 to vcc+0.3 v i o output current 20 ma p d power dissipation 1 w
dc and ac parameters m41t81 22/30 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. figure 14. ac measurement i/o waveform table 7. operating and ac measurement conditions (1) 1. output hi-z is defined as the point where data is no longer driven. parameter m41t81 supply voltage (v cc ) 2.0 to 5.5v ambient operating temperature (t a ) ?40 to 85c load capacitance (c l ) 100pf input rise and fall times 50ns input pulse voltages 0.2v cc to 0.8 v cc input and output timing ref. voltages 0.3v cc to 0.7 v cc table 8. capacitance symbol parameter (1) (2) 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. min max unit c in input capacitance 7 pf c out (3) 3. outputs deselected. output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc
m41t81 dc and ac parameters 23/30 figure 15. power down/up mode ac waveforms table 9. dc characteristics sym parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). min typ max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current switch freq = 400khz 400 a i cc2 supply current (standby) scl,sda = v cc ? 0.3v 100 a v il input low voltage ?0.3 0.3v cc v v ih input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 3.0ma 0.4 v output low voltage (open drain) (2) 2. for irq /ft/out/sqw pin (open drain) i ol = 10ma 0.4 v pull-up supply voltage (open drain) irq /out/ft/sqw 5.5 v v bat (3) 3. stmicroelectronics recommends the rayovac br1225 or br1632 (or equivalent) as the battery supply. battery supply voltage 2.5 (4) 4. after switchover (v so ), v bat (min) can be 2.0v for crystal with r s = 40k ? . 33.5 (5) 5. for rechargeable back-up, v bat (max) may be considered v cc . v i bat battery supply current t a = 25c, v cc = 0v oscillator on, v bat = 3v 0.6 1 a table 10. crystal electrical characteristics sym parameter (1) (2) 1. externally supplied. stmicroelectronics recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thru-hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crystal for industrial temperatur e operations. kds can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. load capacitors are integrated within the m41t81. circuit board layout considerations for the 32.768khz crystal of minimum trac e lengths and isolation from rf generating signals should be taken into account. min typ max units f o resonant frequency 32.768 khz r s series resistance 60 k ? c l load capacitance 12.5 pf ai00596 v cc trec tpd v so sda scl don't care
dc and ac parameters m41t81 24/30 figure 16. bus timing requirements sequence table 11. power down/up ac characteristics symbol parameter (1) (2) 1. v cc fall time should not exceed 5mv/s. 2. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). min typ max unit t pd scl and sda at v ih before power down 0 ns t rec scl and sda at v ih after power up 10 s table 12. power down/up trip points dc characteristics sym parameter (1) (2) 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). min typ max unit v so battery back-up switchover voltage v bat ? 0.80 v bat ? 0.50 v bat ? 0.30 v ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
m41t81 dc and ac parameters 25/30 table 13. ac characteristics sym parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). min typ max units f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 600 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:dat data setup time 100 ns t hd:dat (2) 2. transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of scl. data hold time 0 s t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1.3 s
package mechanical information m41t81 26/30 6 package mechanical information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com .
m41t81 package mechanical information 27/30 figure 17. so8 ? 8-lead plastic small package outline 1. drawing is not to scale. table 14. so8 ? 8-lead plastic small outline (150 mils body width), package mechanical data symbol millimeters inches typ min max typ min max a 1.75 0.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k0808 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
part numbering m41t81 28/30 7 part numbering for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. table 15. ordering information scheme example: m41t 81 m 6 e device type m41t supply voltage and write protect voltage 81 = v cc = 2.0 to 5.5v package m = so8 temperature range 6 = ?40c to 85c shipping method for so8: e = ecopack? package, standard package f = ecopack? package, ta pe & reel 24mm packing
m41t81 revision history 29/30 8 revision history table 16. revision history date revision revision details december 2001 1.0 first issue 21-jan-02 1.1 fix table footnotes ( ta b l e 9 , ta b l e 1 0 ) 01-may-02 1.2 modify reflow time and temperature footnote ( ta b l e 6 ) 05-jun-02 1.3 modify data retention text, trip points ( ta b l e 1 2 ) 10-jun-02 1.4 corrected supply voltage values ( ta bl e 6 , ta bl e 7 ) 03-jul-02 1.5 modify dc characteristics, crystal electrical table footnotes, preferred default values ( ta b l e 9 , ta bl e 1 0 , ta b l e 5 ) 11-oct-02 1.6 add marketing status (figure 2; ta b l e 1 5 ); adjust footnotes ( figure 2 ; ta b l e 9 ) 21-jan-03 1.7 add embedded crystal package option (figure 1, 3 , 23 ; table 16 ); modified pre-existing mechanical drawing ( figure 17 ; ta b l e 1 4 ). 05-mar-03 1.8 correct dimensions (table 16 ); remove snaphat ? package option 12-sep-03 2.0 updated disclaimer, v2.2 template; add sox18 package (figure 2, 4 ; ta b l e 1 5 ) 27-apr-04 3.0 reformatted; update characteristics (figure 4 , 3 , figure 3 , figure 10 , figure 13 , ta b l e 1 , ta b l e 6 , ta b l e 9 , ta b l e 1 2 , ta b l e 1 5 ) 17-jun-04 4.0 reformatted; add lead-free information; add dual footprint connections (figure 5 ; ta b l e 6 , ta b l e 1 5 ) 7-sep-04 5.0 update footprint and maximum ratings (figure 5 ; ta bl e 6 ) 13-sep-04 6.0 update max ratings ( ta b l e 6 ) 03-jun-05 7 remove sox18 and sox28 references (features summary, figure 1 ; ta b l e 1 , ta b l e 6 , ta b l e 1 0 , ta b l e 1 5 ) 12-jul-2006 8 changed document to new template; updated package mechanical data in section 6: package mechanical information ; small text changes for entire docum ent; ecopack compliant.
m41t81 30/30 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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